1. Field of the Invention
The present invention relates to a technology for improving circuit delay of a target circuit by modifying the target circuit and executing a delay analysis of the modified target circuit repeatedly until timing closure is achieved.
2. Description of the Related Art
The development of semiconductor process technology in recent years has led to an increased impact of statistical factors (such as process variation) on the fabrication of very large scale integration (VLSI) circuits. This necessitates in the design of VLSI circuits, for the fabrication of circuits achieving required performance with high yield, a technology for improving circuit delay by taking into account the effect of such statistical factors.
Conventionally, statistical static timing analysis (SSTA) has been proposed in which variations of delay in an integrated circuit (IC) is treated as statistics to calculate delay distribution of the IC. Such a technology is disclosed in, for example, “An Overview of Statistical Timing Analysis” by Shuji Tsukiyama at the 18th workshop on circuits and systems in Karuizawa, Apr. 25-26, 2005. There has been also proposed a method of accurately estimating a slack value by statistically calculating the slack value as a probability distribution in the calculation of delay distribution of an IC. Such a technology is disclosed in, for example, “A Study of the Model and the Accuracy of Statistical Timing Analysis” by Izumi NITTA et al, Singaku-Gihou, IEICE technical report, VLD2005-71, ICD2005-166, DC2005-48 (2005-12).
However, with the conventional technologies, it is difficult to identify which path in the IC should be modified to improve timing of the IC, because the entire IC is statistically analyzed. This necessitates a redesign of the circuit and results in an increased load on a designer and a longer designing period.
On the other hand, all paths in the IC can be improved by static timing analysis (STA) so that the slack value of each path exceeds a target value. However, even when the slack value of each path is improved, timing of the IC may be unimproved due to the nature of the statistical analysis. This necessitates a redesign of the circuit and results in an increased load on a designer and a longer designing period.